1. Field of the Invention
The present invention relates to line interface devices and, in particular, to a high speed latch transceiver having a master stage driven by a clock signal received from an internal clock generator and a slave stage driven directly by an external clock input.
2. Discussion of the Prior Art
A data transceiver (TRANSmitter/reCEIVER) is a read/write terminal capable of transmitting imformation to and receiving information from a transmission medium. A transceiver typically includes a line driver stage and a receiver stage. The line driver amplifies digital signal outputs from a computer system so that the signals can be properly transmitted on the transmission medium. Conventional line drivers usually include level shifting capability to provide compatibility with different integrated circuit technologies (e.g., TTL) that might be used in the computer's internal logic. The receiver is typically a differential amplifier that receives signals from the transmission medium and provides an output representative of digital information received from the medium.
Transceiver circuits may be designed for general-purpose applications or may be designed for a more specific, industry standard data-communications configuration.
One such industry standard is the so-called IEEE 896.1 Futurebus+ standard. The Futurebus+ standard provides a protocol for implementing an internal computer bus architecture.
FIG. 1 shows the hierarchy of bus levels utilizable in a Futurebus+ system.
FIG. 2 shows the positioning of a data transceiver between the backplane bus of a Futurebus+ system and the data bus of a processor internal to that system to facilitate communications between the processor and the rest of the system.
FIG. 3 shows a conventional latching transceiver 10 utilizable in Futurebus+ applications. The latching transceiver 10 is, essentially, a master/slave edge-triggered flip-flop that includes an input buffer 12 that transfers input data A to a master latch 11 via a master CMOS transmission gate 16 when the clock CK is low. When clock signal CK goes high, data stored by the master latch 11 is transferred to a slave latch 18 via a slave CMOS transmission gate 20. Also when clock signal CK goes high, data stored by the slave latch 18 is provided at the output B of latch transceiver 10 via output driver stage 22.
The propagation delay T.sub.pHL of the latch transceiver 10 for a high to low transition of clock CK may be represented as follows: ##EQU1## where the driver 22 high to low delay t.sub.pHL =3ns.
The propagation delay T.sub.pLH for a low to high transition of clock CK may be represented as follows: ##EQU2## where the driver 22 low to high delay t.sub.pLH =4ns.
In both of the above cases, the gate propagation delay T.sub.G is taken to be 1ns. Of course, T.sub.G is process and device geometry dependent and will vary with changes in these parameters. The 1ns propagation delay represents a typical number for a given process. Under worst case conditions (e.g. ambient temperature T.sub.A =70.degree., supply Vce=4.5V and sheet resistance=20%), the 1ns figure could double.
These propagation delays are unacceptably slow for Futurebus+ applications. Furthermore, the FIG. 3 transceiver design is overly temperature dependant, because the transmission gates work poorly when temperature increases.